Generally, electric power should be continuously supplied in order to store data as volatile memory in a DRAM. When electric power is instantly disconnected, data of a RAM may be destroyed because a memory cell of a DRAM is designed based on small charged electrons for storing charged electric power. If these charged electrons are not continuously recharged, the previously charged power can be destroyed.
A refresh operation refers to a recharging process of a cell of a memory chip. In every refresh cycle, memory cells of a row can be charged. Although the refresh operation is performed by memory control of the system, several chips are designed to perform a self-refresh operation.
For example, a DRAM has a self-refresh control circuit so as to perform a self-refresh operation without a Central Processing Unit (CPU) or an external refresh circuit. The self-refresh method to reduce power consumption has been used in a portable computer.
A conventional DRAM performs a refresh operation frequently because DRAM is volatile and has a short refresh cycle. As a result, frequent refresh operation increases power consumption and degrades performance.
Generally, a ferroelectric random access memory (FeRAM) has attracted considerable attention as a next generation memory device because it has a data processing speed as fast as a DRAM and conserves data even after the power is turned off.
FeRAM having structures similar to the DRAM may include capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of ferroelectric substance in which data is not deleted even after an electric field is eliminated.
A one-transistor 1-capacitor (1T1C) type unit cell of conventional FeRAM comprises a switching element configured to perform a switching operation depending on a state of a word line and connect a bit line to a nonvolatile ferroelectric capacitor, and a nonvolatile ferroelectric capacitor connected between a plate line and one end of switching element. Switching element is a NMOS transistor whose switching operation is controlled by a gate control signal.